Project Description

Our gratitude goes to our sponsor, Bob DeLong at Wulfsberg Electronics, for providing us with this project. The synthesizer project involves creating a phase-locked loop (PLL) with an 80 KHz step size that will be a part of a larger frequency synthesizer that Wulfsberg Electronics will be designing and producing.

Our project will be broken down into several major parts: programming a PLL chip, using a microcontroller for communicating with the PLL chip, and designing a loop filter, VCO, and buffer amplifier. The finished project will be completed and delivered to Wulfsberg Electronics by May 2, 2008 and shall include the following:

• PLL design with an 80 KHz step size and a frequency range of 328 - 482 MHz,
• Final hardware implementation on a PCB board and thoroughly tested,
• Several alternative hardware designs built and tested on PCBs,
• Noise specifications that meet or exceed those set forth by the sponsor.

Upon completion of the project we will deliver a final report containing all of our work. Included in this will be the microcontroller software, the device schematic, the PCB layout, the test board and a white paper. The microcontroller software will include all routines necessary for the setup and proper function of the PLL and MCU chips used. Schematics, designed using CadStar, will be provided for each test circuit. The PCB layout, which will include all test circuits, will be provided. If requested, the physical board will also be delivered. A final white paper with all calculations, assumptions, explanations and theories will be submitted either electronically, in print, or both.